1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device of master slice approach which includes bipolar transistors and the like as basic elements.
2. Description of the Prior Art
A first conventional example of a master slice approach which includes a bipolar transistor element as a basic element is shown in FIG. 1.
In the first conventional example, peripheral cells 12 are arranged in a peripheral portion of a semiconductor chip 11, and internal cells 13 as island regions are surrounded by the peripheral cells 12. Therefore, portions around the internal cells 13 constitute wiring regions 14.
In one island-like internal cell 13, npn bipolar transistor elements 15, pnp bipolar transistor elements 16, MIS capacitive elements 17, resistive elements 18 formed by impurity diffusion layers, and the like are formed, as shown in FIG. 2. In each internal cell 13, the elements 15 to 18 and the like are optimally arranged in accordance with its application purpose.
A master slice including a bipolar transistor as a basic element is not limited to the bipolar master slice described above, but can be exemplified by a Bi-MOS master slice, a Bi-CMOS master slice (Nikkei Electronics, 1988.4.18 (No. 445), pp. 227-241). All these conventional master slices have the structures shown in FIGS. 1 and 2.
In the first conventional example described above, each internal cell 13 is optimized for a specific purpose, but does not have versatility. The region of the internal cell 13 and the wiring regions 14 are fixed. For this reason, systematic, optimal circuit design cannot be achieved, and a wasteful region is undesirably formed.
In addition, the wiring regions 14 are regions for only wiring, and the elements 15 to 18 are not formed in the wiring regions 14 at all. Therefore, a high integration level cannot be obtained in the first conventional example described above.
As is apparent from FIG. 2, the bipolar transistors 15 and 16 are not generally formed to be adjacent to the resistive elements 18. For this reason, the layout of the elements 15 to 18 cannot comply with a descriptive image of circuit design. Therefore, it is not easy to obtain an optimal circuit layout.
In addition, when each resistive element 18 is formed as a diffusion resistor in a semiconductor substrate, the integration level of the basic elements 15 to 17 except for the resistive elements 18 is naturally low.
When the resistive elements 18 are formed as diffusion resistors in the semiconductor substrate, the layout of the resistive elements 18 and their resistances cannot be optimized in individual circuits. For example, several resistive elements 18 are required in a master slice to obtain one resistive element in the circuit design description. As a result, the region of the resistive elements 18 and the region of the basic elements 15 to 17 except for the resistive elements 18 are unbalanced, and effective utilization of the total region for the basic elements 15 to 18 is undesirably prevented.
Since the layout of the resistive elements 18 and their resistances cannot be optimized in the individual circuits, it is not easy to design the circuit layout.
Other master slices shown in FIGS. 3 and 4 are conventional master slice examples including bipolar transistor elements and MOS transistor elements as basic elements.
The second conventional example shown in FIG. 3 includes bipolar transistor elements as major elements. Blocks of bipolar transistor elements 21 constituting an operational amplifier and blocks of MOS transistor elements 22 constituting an analog switch are formed on a semiconductor chip 11.
The third conventional example shown in FIG. 4 comprises MOS transistor elements as major elements. A block of MOS transistor elements 23 constituting a gate array and blocks of bipolar transistor elements 24 constituting an input/output circuit are formed on a semiconductor chip 11.
Although the second and third conventional examples are optimized for specific application purposes, a ratio of the number of bipolar transistor elements 21 and 24 to the number of MOS transistor elements 22 and 23 is fixed. For this reason, versatility in circuit design is limited in the second and third conventional examples described above.
A Bi-CMOS device or the like generally comprises at least a MOS transistor element, a MIS capacitive element, and a resistive element.
FIG. 5 shows still another example of a semiconductor device obtained by wiring a Bi-CMOS master slice as a fourth conventional example of the master slice. In order to manufacture this semiconductor device, a p-type well 26 is formed in an n-type Si substrate 25, and an SiO.sub.2 film 27 is then formed as a field oxide.
The surface of the Si substrate 25 is oxidized to form an SiO.sub.2 film 28 serving as a gate oxide and an SiO.sub.2 film 29 serving as an insulator film of a MIS capacitive element. A resist film (not shown) is patterned, and an impurity is ion-implanted to form an n.sup.+ -type region 31 serving as one electrode of the MIS capacitive element.
A first poly-Si layer is patterned to form a poly-Si layer 32 serving as a gate electrode and a poly-Si layer 33 serving as the other electrode of the MIS capacitive element.
The surfaces of the poly-Si layers 32 and 33 are oxidized to form SiO.sub.2 films 34 and 35. In this state, an impurity is ion-implanted to form n.sup.+ -type regions 36 and 37 serving as source/drain regions and an n.sup.+ -type region 38 serving as an electrode take-off connection of the n.sup.+ -type region 31.
A second poly-Si layer (not shown) is patterned to form resistive elements at predetermined positions.
Thereafter, an interlayer insulator 41 and electrode windows 42 to 45 are formed, and A1 wiring layers 46 to 49 are patterned to form a MOS transistor element 51, a MIS capacitive element 52, and a resistive element (not shown).
In the conventional fabrication method described above, the poly-Si layers 32 and 33 are made of the first poly-Si layer, and the poly-Si layer 32 is used as an ion-implantation mask for forming the n.sup.+ -type regions 36 and 37. Therefore, the n.sup.+ -type region 31 under the poly-Si layer 33 cannot be simultaneously formed with the n.sup.+ -type regions 36 and 37.
For this reason, as described above, lithographic and ion-implantation steps for forming the n.sup.+ -type region 31 are required. Therefore, the above method has a large number of steps.